Author:
R.Gowri Shankar1 , D.R. Ananthi, 2Published in
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ABSTRACT:
Approximate computing significantly enhances digital circuit performance by reducing hardware complexity, especially in error-resilient applications like DSP, multimedia, and machine learning. To improve these applications, particularly Convolutional Neural Networks, we designed a truncation-based Booth multiplier using multi-level compressors such as 4:2, 5:2, and 6:3 counters. We created a compensation circuit through selective Karnaugh map modifications to handle carries from truncated parts. By mapping efficiently, we reduced hardware and output errors simultaneously. We introduced Truncated and Approximate Booth Multipliers using Compressors and Counters (TABM-CC), offering multiple designs based on truncation factor www, balancing power and accuracy. Our proposed TABM-CC architecture outperforms existing multipliers in both accuracy and Area-Power efficiency. Parallel multipliers, vital in DSPs, CPUs, and multimedia systems, benefit significantly from this approach. Since most CPUs contain multipliers in critical signal paths, our design reduces delay and complexity, optimizing real-time digital processing in high-performance and low-power systems.
INTRODUCTION:
Parallel multipliers serve as key components in digital hardware, including SoCs and GPUs. They directly influence system performance, prompting researchers to continuously improve their speed, power efficiency, and size. In typical binary multiplication, designers follow a four-step process: digit recoding, digit-wise multiplication, reduction of partial products, and final carry-propagate addition. Full adder (FA)-based architectures, while common, suffer from cascading delays and high gate counts. To address this, we employed compressor networks—particularly 5:2 and 7:2 designs—to reduce latency and power consumption. We optimized these compressors by enhancing horizontal carry paths and introducing neutral output states, which significantly reduced vertical signal load. For instance, our 5:2 compressor achieved a 303-ps delay with fewer than three XOR gate delays. This optimization led to a 7:2 compressor with a four-XOR latency. These speed gains, paired with low power and compact area, make our designs ideal for energy-efficient real-time multipliers in modern digital applications.
