SCALABLE FPGA ARCHITECTURE FOR VEDIC MULTIPLIER USING HNFG GATE

Abstract : Reversible digital technology is paving the way for faster processing speeds and reduced power consumption, making it a promising approach for modern computation. This study introduces the construction of 8-, 16-, 32-, and 64-bit multipliers leveraging the high-speed capabilities of the proposed HNFG gate adder. The design integrates carry-save adders, KoggeStone adders, and HNFG adders with the Vedic multiplier to achieve enhanced efficiency. By utilizing reversible logic gates, the proposed design improves computational performance while minimizing area and power consumption. The implementation focuses on achieving high operational speeds through optimized multiplier and adder units, which are critical for improving the accuracy and efficiency of arithmetic operations. A comparative analysis between the conventional approach and the HNFG-based Kogge-Stone adder highlights the significant performance gains of the proposed method. The simulation and synthesis of the designs are carried out using Xilinx 14.7, demonstrating superior speed and efficiency of the HNFG-based multiplier-adder architecture over traditional method

Keyword: Keywords: VEDIC MULTIPLIER, KOGGE STONE ADDER, CARRY SAVE ADDER, HNFG GATE