Author : R.Gowri Shankar1 , D.R. Ananthi, 2
Page No: 163-182
Abstract : Approximate computing is a promising technique to elevate the performance of digital circuits which curtail the hardware requirements by exploiting the inherent error resilience of certain applications such as digital signal processing, multimedia and machine learning. Approximate multipliers and other approximation techniques can be integrated to increase the performance of applications such as convolutional Neural Networks. In the proposed work, a truncation based Booth multiplier is designed based on multi-level compressors such as 4:2, 5:2 and 6:3 counter. A compensation circuit is generated by selective modifications in k-map to circumvent the carry appearing from the truncated part. By efficient mapping, hardware pruning and output error reduction is achieved simultaneously. In the quest of power and accuracy tradeoff, Truncated and Approximate Booth Multipliers using compressors and counters (TABM-CC) are proposed with a range of designs based on truncation factor w. When compared with the state-of-the-art multipliers, TACBM outperforms in terms of accuracy and Area-Power savings.
Keyword Truncated and Approximate Booth Multipliers using compressors and counters (TABM-CC), Compressors, Counters, Digital Signal Processing

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