Page No: 183-201
Abstract : Timing error is now getting increased attention due to the high rate of error-occurrence on
semiconductors. Even slight external disturbance can threaten the timing margin between
successive clocks since the latest semiconductor operates with high frequency and small supply
voltage. To deal with a timing error, many techniques have been introduced. Nevertheless,
existing methods that mitigate a timing error mostly have time-delaying mechanisms and too
complex operation, resulting in a timing problem on clock-based systems and hardware
overhead. In the proposed work a novel timing-error-tolerant method that can correct a timing
error instantly through a simple mechanism is demonstrated. By modifying a clock in a flip-flop,
the proposed system can recover a timing error without the loss of time in the clock-based
system. Furthermore, in order to reduce power consumption in the stages were operation is
not performed clock gating mechanism is used to reduce the unwanted transition. Look-Ahead
Clock Gating (LACG) computes the clock enabling signals of each FF one cycle ahead of time,
based on the present cycle data of those FFs on which it depends. It has however a big
advantage of avoiding the tight timing constraints of earlier methods, by allotting a full clock
cycle for the enabling signals to be computed and propagate to their gaters.