IMPLEMENTATION OF POLAR CODES USING VERILOG HDL

Polar codes are error correction codes that are widely used in communication systems. Polar codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Polar decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximuma- Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder side. The proposed system has designed by using Verilog HDL and this design was simulated in Xilinx ISE 13.2. 5Gpeakmobile broad band data rates are expected to be around20Gbps. Beyond5G systems are expected to operate at Terabit/s data rates. Today’s most advanced polar code implementations currently deliver only around 5Gbps. Therefore, Turbo codes and LDPC codes that played key enablers in 3Gand 4G systems are already unproven for many new 5G applications. Polar code is believed as prominent breakthrough in 5G. It guarantees apical performance for 5G scenarios and hence it is considered as a promising candidate for the5GNewRadio. This work accentuates on the suitability of polar codes for the 5G scenarios.

Polar Codes, VLSI, VerilogHDL, MAP Algorithm, SISO Decoder, 5G, Interleaver.

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